The present application relates to systems, devices and methods for substrate patterning and inspection using charged particle beams; and more particularly to alignment and registration of charged particle beam columns with respect to a semiconductor wafer or other substrate, and/or to previously written patterns thereon.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
FIG. 2A shows an example of a wafer 200 being scanned by multiple electron beams 204 (e-beams) emitted by respective beam columns 206 (e-beam columns, see FIG. 2B). A patterned or unpatterned wafer 200 (or other substrate) is independently and simultaneously scanned by multiple columns 206 to either write or inspect the wafer 200. Columns 206 can be separately controlled—e.g., with different deflections and different blanking timings. (One of ordinary skill in the arts of charged particle beam substrate processing will recognize that a wide variety of other control options are available per-column.) When writing a wafer 200 (or other substrate), the columns 206 emit electron beams 204 at a power level sufficient to change certain properties of a resist layer coated on the substrate so that after the resist is developed (in ways similar to developing a photographic film), etch steps can take place. When inspecting a wafer 200, the columns 206 emit electron beams 204 (generally at a lower power level than when writing) and detect an image of the substrate surface caused by the resulting scattered electrons. Individual columns 206 are able to target a portion 202 of the substrate surface with their respectively emitted beams 204.
In preferred embodiments, the array of electron beam columns 206 is stationary, the stage holding the wafer 200 moves back and forth, and the electron beam column 206 moves the beam 204 across the wafer 200 to write or to perform imaging (the latter during, e.g., alignment or registration, or wafer inspection). The beam motion across the wafer 200 can be, for example, vector scanning to a target feature or “care-area” containing a target feature, and raster scanning across the target feature while writing or inspecting. Preferably, each column 206 has its own detector and control computer. Vector-raster scanning, care-areas, and use of multiple control computers local to respective columns are disclosed in U.S. Pat. No. 9,466,463, which is incorporated herein by reference.
As mentioned above, after e-beams 204 write features to a resist-coated substrate, the substrate is typically treated with resist development followed by etch steps in order to complete the writing process. (Herein, the immediate results of e-beam writing are called “features”, and continue to be called “features” throughout the patterning process, including after non-radiative steps, e.g., develop and/or etch.)
Herein, in some instances, develop and/or etch and/or other steps are not explicitly described with respect to lithography and inspection. It will be understood by those skilled in the art that these steps (e.g., develop and etch) are performed when appropriate, and can be omitted from discussion for clarity of explanation. Inspection (also referred to herein as “imaging”) of features on the substrate occurs after writing.
Generally, in resist development, the resist coated substrate is immersed in or otherwise in contact with liquid chemical (resist developer solution), followed by rinsing. Certain properties of the resist are changed by e-beam exposure such that the e-beam-exposed area either becomes soluble in resist developer solution (“positive” resist, which is insoluble until exposed to e-beams) or becomes insoluble in resist developer solution (“negative” resist, which is soluble until exposed to e-beams). When a positive resist is exposed to e-beams, the unexposed portions remain insoluble, and will be left intact after the substrate is washed with resist developer solution. When a negative resist is exposed to e-beams, the unexposed portions remain soluble, and will be washed away by resist developer solution, leaving the e-beam-exposed portions intact.
As a result of resist development, a pattern will emerge on the substrate comprising many features written by the e-beam lithography tool. E-beams can then be used to inspect these features for defects. Inspection after development is also known as after-develop inspection (ADI).
Etch follows resist development. In etching, material exposed to the etch environment is removed, while material protected by developed resist is not etched. Inspection after etch is also known as after-etch inspection (AEI).
Both lithography (optical, e-beam and otherwise) and etch can introduce process-dependent defects to the patterned substrate. Generally, process-induced defects are defects introduced during wafer handling, resist spin and heating, lithography, resist development, etch, deposition, inspection, implantation, thermal processing, and chemical-mechanical polishing.
FIG. 2B shows an example of a wafer 200. The wafer 200 (or other substrate) is written or image data is gathered (beams are emitted) using columns 206 (columns 206 are shown via their center positions, represented here as plusses). Example die 208 size and column 206 center-to-center spacing 210 (column separation) are shown. A regular grid of columns 206 can use different spacing 210 in different (orthogonal) directions. Die 208 size and column separation 210 are not required to (and generally, will not) correspond. Column separation 210 generally corresponds to the substrate area 202 targetable by beams 204 emitted from respective columns 206.
Wafer 200 patterning and inspection using electron beams 202 can be made highly parallelized by using multiple electron beams 202. Electron beams 202 emitted by columns 206 in a multiple column 206 array can be independently and simultaneously scanned across the wafer 200 using electrostatic deflectors, preferably using distributed column control systems (e.g., local column control computers, as described hereinabove with respect to FIG. 2A).
The multiple column 206 array comprises electron beam columns 206 arranged in a regular grid. For example, column 206 arrays with center-to-center column spacing 210 of 30 mm×30 mm have been implemented, though other column spacings 210 (e.g., 24 mm×33 mm) can also be used.
A column 206 can be configured to scan a die 208 (IC), part of a die 208, or multiple dies 208 during inspection. Each die 208 can be scanned by one or more columns 206, depending on the column 206 writing area 202. The “writing area” is the area to which the column 206 can deflect its beam to obtain images or write pattern (depending on the capabilities of the column 206), taking into account wafer stage movement.
FIG. 2C schematically shows an example of a miniature e-beam column 220 comprising an electron gun 222, including an electron source and electron gun lens; deflection assembly 224; and main lens 226. A miniature e-beam column 220 can also include, for example, deflectors, apertures, blankers, other electron-optical components, column control electronics, electron detectors or other sensors, and/or other elements for column 220 operation, maintenance, and testing.
FIG. 2D shows an example of an e-beam substrate patterning and/or inspection system 230. This e-beam system comprises an array 232 of miniature e-beam columns 220, as well as a wafer loading/unloading mechanism 234 and a wafer stage 236. Other sub-systems that are used for substrate patterning and/or inspection include control electronics, vacuum systems, alignment systems, vibration isolation and magnetic shielding.
FIG. 2E shows an example of a uni-directional (1-D) layout process using both optical and electron beam lithography. “1-D” refers to 1-D gridded design rule.
Apparent resolution limits of optical systems have resulted in a process of simplification of integrated circuit layouts in order to ensure printability as design rules shrink. At one time, pattern design common wisdom allowed lines to run in virtually any direction. Later, pattern design was largely restricted to perpendicular lines, often referred to as Manhattan geometries. As feature sizes shrink further, optical pattern design can advantageously be restricted to lines running in a single direction, with features perpendicular to the 1-D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool comprising an array of columns—for example, electrostatically controlled miniature electron beam columns.
It is common to pattern the layout of 1-D designs by separating the 1-D design layout database into lines and cuts. A 1-D layout 242 is separated in the design layout database into a “line pattern” 244 and a “cut pattern” 246. The design layout database contains the information needed by lithography tools to pattern one or more layers on a substrate. A line pattern 244 generally comprises an array of unidirectional lines 248. Cut patterns 246 generally comprise line-cuts and holes 250.
Line patterns 244 are typically written by an optical lithography system, which can be followed by other process steps to increase the density of lines on the substrate 252. Cut patterns can be written by e-beam lithography 254 (e.g., miniature e-beam column lithography). Such use of e-beam lithography (which can also write via holes and contact holes) is also called complementary e-beam lithography, or CEBL. The combination of the line-forming process followed by line-cuts written with CEBL to pattern a substrate layer is called complementary lithography. Optical masks for use in complementary lithography can be made without any information about the cuts. CEBL generally uses only the cut database.
The optically-printed 252 line pattern 248 and the e-beam-written 254 cut pattern 250 combine to form a 1-D layer 256 on the substrate that corresponds to the 1-D pattern 242 specified by the design layout database. Separating the pattern 242 this way uses the respective unique capabilities of optical lithography and e-beam lithography. Optical lithography can efficiently print uniform parallel lines over a large area of a substrate. E-beam lithography inherently can write smaller features more effectively than an optical lithography tool.
FIG. 2F schematically shows an example of a 1-D layout pattern 260. Here, line patterns 244 (printed by an optical lithography system) are shown as horizontal lines 262, while cut patterns 246 (written by, for example, a CEBL system) are shown as (generally, much shorter) vertical lines 264. Example spacing and line/cut widths are shown; other spacing and widths can be used (e.g., in more advanced processes).
FIG. 2G shows an example of a complementary lithography process 270. One or more multiple, miniature-column, e-beam lithography systems 230 are used in combination with an optical lithography system 272 and other wafer processing tools (e.g. resist development and etch tools) to pattern a wafer layer. Here, optical lithography tools 272 expose 274 1-D lines 248. (Several other processing steps not shown in this figure typically follow, e.g., involving resist and hard masks. Every other mention of “mask” herein refers specifically to optical masks, i.e., masks used by an optical lithography system to expose a pattern.) E-beam lithography systems are then used to write 254 patterns 250 such as line cuts and holes. An etch tool 276 is used to etch 278 the resist, exposing the features written 254 by the e-beam tool 230.
Generally, e-beam lithography systems can write with higher resolution than optical lithography systems. However, in e-beam lithography, features are generally written serially (by individual beams), one at a time, as opposed to lithographic printing of a much larger area with optical tools using masks.
FIGS. 2H and 2J show examples of prior art registration marks. These marks can also be used as alignment marks.
FIG. 2I shows an example of prior art alignment mark placement. Chip marks 280 are located within dies, while global marks 282 are located on the stage. Note that beam x-axis 284 and beam y-axis 286 are not necessarily parallel to (respectively) stage x-axis 288 and stage y-axis 290.
Wafer or substrate “alignment” is defined herein as the action of positioning a wafer or other substrate with respect to the coordinate system of a lithography, inspection, or other process tool. Marks on the wafer or substrate that facilitate this process are called “alignment marks” or “alignment targets”.
“Pattern registration” (or “registration”) is defined herein as positioning a subsequent pattern on the wafer or substrate with respect to a previous pattern on the wafer or substrate. Marks on the wafer or substrate that facilitate this process are called “registration marks” or “registration targets”. “Pattern overlay” is the measured error resulting from inaccuracy of the registration process.
Generally, registration errors increase as distance from alignment and registration targets increases, over time, and as beam deflections are performed. Improving locality (in space and time) of registration to active material processing and imaging locations tends to reduce accumulated registration drift, reduce pattern overlay errors and improve process and imaging fidelity, thereby improving yield.
Cross-like or other fiducial marks have historically been used to register and/or align a single column. FIG. 2H is an example of a previously used wafer alignment mark. FIG. 2I is an example of a previously used reticle alignment mark.